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NCL30051
? Low pin-count of controller combines strong feature
set
? Low external component count
? ZVS of the second stage FETs without any tuning
requirements
? High efficiency facilitates improved thermal
performance
? Low EMI and easy filtering due to fixed frequency
? Facilitation of synchronous rectification control design
? Easier design of magnetic components (esp. Resonant
transformer and inductor)
While the above listed benefits make this approach a
very interesting proposition for many isolated applications
with PFC front-end, it has to be implemented with some
additional considerations.
The fact that the output regulation is achieved by
adjusting the PFC output voltage, places additional limits
on the PFC stage that is not needed in the traditional
approach. Depending on the application and output
requirements, this may not be much of a constraint.
However, if the output variation requirements are
significant, the PFC stage may not have enough dynamic
range to provide sufficient output power control.
The other consideration is related to the response time to
any output variations. In a true 2-stage conversion, the
decoupling of the two stages allows a better transient
response. In that case the PFC converter is constrained to
a bandwidth much below the line frequency (typically <
20 Hz), whereas the second stage can be optimized to have
a very fast dynamic response. In the NCL30051
application, the second stage has no independent output
regulation ability, so the dynamic response is constrained
by the PFC stage bandwidth. This limitation means that the
approach is not suited for very fast-transient loads.
However, a large number of applications (such as LED
drivers and battery chargers) can easily accept the response
times offered by the NCL30051 approach.
Output voltage ripple is another consideration when
designing with the NCL30051. The low frequency ripple
on the PFC output stage is determined by the size of the
PFC capacitor. With no compensation in the second stage,
the final output voltage ripple is simply a scaled version of
the PFC output ripple determined by the fixed ratio of the
second stage. Normally this type of ripple is not a concern
for lighting applications as the ripple frequency
(100/120 Hz) is above the eye response frequency or in the
case of fixed output LED power supplies, there are
secondary side constant current regulators that further
reduces the ripple.
Finally, hold-up time is another matter to be considered
when using this fixed-ratio converter approach. When the
input voltage droops, the output of the PFC starts dropping
at a rate determined by the bulk capacitance value and the
load current. The output voltage follows this discharge rate
with a fixed ratio. By increasing the bulk capacitance
value, this discharge rate can be slowed down increasing
hold-up time . However, this approach has practical limits
and is not recommended for applications requiring a long
hold-up time with no output voltage variation.
Figure 2 illustrates a typical NCL30051 2-stage
converter implementation. As seen in the figure, the
isolated second stage converter output value is processed
by a compensation circuit in the secondary and an error
signal is generated and coupled to the primary using an
opto-coupler. On the primary side, this signal is fed to the
PControl pin of NCL30051 through a reverse ORing diode.
The PControl pin also has a default error signal generated
by the PFC error amplifier. The lower of these two signals
dominates and helps set the fixed ON time for the PFC
block as described in earlier sections. In the intended
implementation, the NCL30051’s PFC error amplifier
should be configured to set the maximum value of the
output voltage and the secondary side feedback should be
allowed to control it lower based on the output conditions.
DESIGN CONSIDERATIONS – POWER STAGE
Given the unique nature of the NCL30051, certain power
stage design considerations are applicable (for PFC and
second-stage) as below. These design considerations are
described for a constant current LED lighting application,
but can also apply to constant voltage applications with
minor variations.
PFC Output (Vbulk) Voltage Range
The minimum bulk voltage setting is dictated by the
requirement that the PFC output voltage be higher than the
peak of the input line voltage at all times. Even though
many lighting applications operate from a single voltage
range which simplifies the analysis, we will consider an
input range of 85-265 Vac which covers most regional
requirements, this means the minimum bulk voltage is set
in the range of 385-400 Vdc. However, if the circuit has to
handle 277 Vac ± 10% input also (as in the case of US
commercial lighting applications), the minimum bulk
setting goes up to 435 Vdc. The maximum bulk setting is
limited by component stress factors and other
considerations. The major constraints are bulk capacitor,
output (boost) diode, boost FET and the NCL30051 voltage
rating.
While other power stage considerations are covered in
the paragraphs below, the application of NCL30051
requires that the bulk voltage be limited to below 600 V
maximum under all conditions. The NCL30051
high-voltage section is rated at 600 V ? this includes pins
HV and HVS. The HBoost and HDRVhi pins see the
highest potential, given by Vbulk+Vcc. In normal
operation the bulk is limited to 540 V based on the derating
criteria. This is the same derating which would be applied
to the 600 V output rectifier in the PFC stage.
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